1. Field of the Invention
The present invention relates to a process for producing a semiconductor device, more particularly, a process for the formation of a contact electrode which is to be placed in ohmic contact with the semiconductor substrate of a semiconductor device, particularly an MIS structure semiconductor device.
2. Description of the Prior Art
In MIS structure semiconductor devices, such as an MOS field effect transistor (MOS FET) and an MOS integrated circuit (MOS IC), the semiconductor substrate must be connected to a ground potential or a back gate bias potential. An MIS structure semiconductor device is, therefore, always provided with a terminal for electrically connecting a current source of a ground potential or a back gate bias potential with the semiconductor substrate. However, the connection of the terminal with the semiconductor substrate, which is formed at the outermost part of the semiconductor device, is sometimes difficult for the reasons explained hereinafter.
FIG. 1 is a cross sectional view of an essential part of a conventional MIS structure semiconductor device. Referring to FIG. 1, a semiconductor element 1 comprises a semiconductor substrate 2 and an insulating film 3 formed on the front surface of the semiconductor substrate 2. A terminal 4 is formed on the insulating film 3 and is used to apply a back gate bias potential or a ground potential to the semiconductor substrate 2. The terminal 4 is hereinafter referred to as a ground terminal. The semiconductor element 1 is mounted on a ceramic package 5. The ceramic body 6 of the package 5 is provided with a metallic layer 8, such as a metallized layer or a molybdenum sheet. The semiconductor substrate 1 is ohmically bonded to the metallic layer 8 through the rear surface of the substrate and a soldering layer 11. A fine wire 9 of, for example, gold is connected between the metallic layer 8 and a terminal 10, hereinafter referred to as an external terminal 10. In addition, a fine wire 9' is connected between the external terminal 10 and the ground terminal 4.
In the structure of the MIS semiconductor device of FIG. 1, the bonding position of the fine wire 9 with the metallic layer 8 should be so selected that the soldering material of the layer 11 does not flow to the bonding position. In addition, there is a considerable difference in height between the bonding positions of the fine wire 9' and the fine wire 9. Because of the facts concerning the bonding position and the height difference mentioned above, the bonding operation is difficult and bonding of wires, particularly fine wires, using an automatic bonding machine is difficult.
It has been proposed in the prior art to ohmically connect the ground terminal mentioned above to a semiconductor substrate and, hence, to eliminate the necessity of the fine wire 9 indicated in FIG. 1. A contact process illustrated by FIGS. 2A through 2F is a variation of the proposed process. FIGS. 2A through 2F are cross sectional views of parts of an N channel MOS IC. In FIG. 2A, on a P type silicon (Si) substrate 2, the borders of a substrate contact region 22 and a semiconductor element region 23 are defined by a field oxide film 21. The semiconductor element region 23 and substrate contact region 22 are separated from each other by the field oxide film 21. A gate oxide film 24 and a gate electrode 25 made of polycrystalline silicon are formed on the semiconductor element region 23.
In FIG. 2B, a photoresist 51 is applied on the P type semiconductor substrate 2 and, then, left on the substrate-contact region 22 by a conventional photolithographic technique. Impurities are implanted by an ion implantation technique using the gate oxide film 24 and the gate electrode 25 as a mask, as illustrated by arrows, so as to form an N.sup.+ type source region 27 and an N.sup.+ type drain region 27'. However, instead of the ion implantation technique, a diffusion technique can be used for the formation of the source and drain regions. When the diffusion technique is used, an oxide film is formed on the substrate-contact region 22 and the semiconductor-element region 23, and polycrystalline silicon is delineated into a gate electrode 25. Subsequently, a photoresist is formed and delineated as indicated in FIG. 2B (c.f. 51) and, then, the oxide film is removed by etching so as to expose parts of the semiconductor element region where the source and drain regions are later formed. Diffusion of the impurities is carried out so as to form the N.sup.+ type source region 27 and N.sup.+ type drain region 27', while leaving the oxide film on the substrate-contacting region 22.
After the formation of the source and drain regions as explained above, a phosphosilicate glass (PSG) layer 26 (FIG. 2C) is formed on an oxide film 41 for suppressing the diffusion of phosphorus from the PSG layer 26. The PSG layer 26 and the oxide film 41 are selectively removed by an etching technique so as to form apertures 28, 28' and 28" (FIG. 2D) for exposing the substrate-contact region 22, the source region 27 and the drain region 27', respectively.
Subsequently, an oxide film 42 is formed on the regions exposed in the apertures 28, 28' and 28" as indicated in FIG. 2E. The oxide film 42 prevents the formation of PN junctions on the exposed regions mentioned above due to out-diffusion of phosphorus in the PSG layer 26 into these regions. Such out-diffusion occurs during a heat treatment which will be explained with reference to FIG. 2F. The heat treatment is carried out so as to control the diffusion or ion-implanted depth of the source and drain regions, and also to melt and round the edges of the PSG layer 26 indicated in FIG. 2D. The oxide film 42 is then removed and contact electrodes of aluminum 32, 32' and 32" and polycrystalline silicon 30, 30' and 30" are formed as indicated in FIG. 2F.
In the process as explained with reference to FIGS. 2A through 2F, the formation of the oxide film 42 is indispensable, and the heat treatment for the oxide film formation deepens the source and drain regions. This process is, therefore, not suitable for the formation of shallow source and drain regions.
Another variation of the known process is illustrated in FIG. 3. A substrate-contact electrode is prepared by short circuiting a PN junction in this variation. An N channel MOS IC illustrated in FIGS. 3 and 4A-C comprises a p type silicon substrate 2, a gate insulating film 12, a gate electrode 13 made of polycrystalline silicon, a PSG layer 14, an N.sup.+ type source region 15, an N.sup.+ type drain region 15', a source electrode 16 made of aluminum and a drain electrode 16' made of a lower layer of polycrystalline silicon and an upper layer of aluminum. The source electrode 16 is ohmically in contact with the silicon substrate 2, because there is no underlying polycrystalline silicon, and further, molten aluminum of the source electrode 16 easily penetrates through the PN junction between the source region 15 and the silicon substrate 2 during a heat treatment for melting the aluminum. A layer 17 containing a high concentration of aluminum is formed due to the aluminum penetration and, therefore, the source electrode 16 is ohmically in contact with the silicon substrate. A substrate-contact electrode is, therefore, produced by the source electrode 16.
The process explained above with reference to FIG. 3, however, involves a problem in causing a discontinuity in the aluminum layer of the source electrode 16, and the MOS IC produced by variation of the process is not reliable in practical use.
Referring to FIGS. 4A through 4C, illustrating the occurrence of the discontinuity mentioned above, a polycrystalline silicon layer 18 is deposited on the surface of silicon substrate 2 including the surface of the source region 15 and the drain region 15'. Thereafter, a photoresist film 19 is selectively formed on the polycrystalline silicon layer 18 so as to expose a region of the layer 18 for the formation of the electrode which is in ohmic contact with the substrate, for example, a region of the layer 18 above the source region 15. The polycrystalline silicon layer 18 is then removed by a plasma etching technique using the photoresist film 19 as a mask. In the removal of the polycrystalline silicon layer 18, it is extremely difficult to precisely terminate the plasma etching at the completion of such removal. The surface of the silicon substrate 2 is, therefore, deeply etched away as illustrated in FIG. 4B, and a concavity 20 is caused to form. When the aluminum layer of the source electrode 16 is deposited on the deeply etched surface of the silicon substrate, the aluminum layer is extremely thin at the vertical wall portions of the concavity 20 as indicated in FIG. 4C and is, therefore, very likely to break.
The reason for formation of the concavity 20 will now be explained. Just before the plasma etching of the polycrystalline silicon layer 18 is completed the exposed polycrystalline silicon layer 18 remains only on the surface of the source region. The surface area of the polycrystalline silicon layer 18 is, therefore, considerably reduced at a time close to completion of the etching as compared to that at the beginning of the plasma etching. Since the plasma etching rate in the vertical direction of a polycrystalline silicon layer is high when the surface area thereof is small, the polycrystalline silicon layer is rapidly and deeply etched in a short period of time. It is, therefore, impossible to precisely terminate the plasma etching when the removal of the polycrystalline silicon layer 18 is completed. Consequently, the concavity 20 is formed. The tendency to form the concavity is especially conspicuous in the so called selective oxidation process used for MOS ICs and MOS LSIs. In the selective oxidation structures, a thick field oxide film 21 is formed by thermal oxidation. The substrate-contacting region and the MOS FET are isolated from each other by an insulation-isolation of the field oxide film 21. In the thermal oxidation, a thick oxide film 21' is formed on the surface of the silicon substrate opposite to the surface, where MOSFETs are formed, and remains on this opposite surface until the final step of producing the MOS ICs. Accordingly, the surface area of the silicon exposed to the plasma gas is very small and, hence, the tendency to form the concavity is conspicuous in the production of the MOS ICs and MOS FETs having the selective oxidation structure. An electrode which is in ohmic contact with a semiconductor substrate from an upper-surface of an MIS structure semiconductor device is hereinafter simply referred to as a substrate-contact electrode.